Method for producing micromechanic sensors and sensors produced by said method

ABSTRACT

Proposed is a method for manufacturing micromechanical sensors and sensors manufactured by this method, where openings are introduced into a semiconductor substrate. After the openings are introduced into the semiconductor substrate, a subsequent temperature treatment is carried out, in which the openings are converted into voids in the depth of the substrate.

FIELD OF THE INVENTION

The present invention relates to a method for manufacturingmicromechanical sensors and micromechanical sensors produced by it.

BACKGROUND INFORMATION

An article of Mizushima et al., Applied Physics Letter, Vol. 77, No. 20,Nov. 13th, 2000, page 3290 ff., already describes a method, in whichvoids are produced in the semiconductor substrate by introducingopenings and carrying out a subsequent temperature treatment. However,these structures are only intended to be used in integrated circuits. Amultitude of other manufacturing processes, in particular the so-calledsacrificial-layer technique, are known for manufacturing sensors. Inthis context, a silicon layer is produced on a sacrificial layer. Thesacrificial layer is then removed again after the silicon layer ispatterned.

SUMMARY OF THE INVENTION

The method of the present invention has the advantage over thebackground art, that a particularly simple method for manufacturingmicromechanical sensors is specified. In this context, themicromechanical sensors constitute sensor elements, which are made ofmonocrystalline silicon. The method is also suitable for the integrationof circuit elements.

In order to ensure that a void is reliably produced, the introducedopenings should be deeper than the diameter. They should preferably havea diameter of less than 1 μm and be deeper than 2 μm. Sufficiently hightemperatures ensure that the mobility of the silicon atoms on thesubstrate is sufficient. The actual sensor elements are then formed byfurther processing steps. In this context, the deposition of an epitaxylayer and the introduction of dopants are advantageous.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 through 4 show a first process sequence.

FIGS. 5 through 8 show a further process sequence for producing voids.

FIG. 9 shows a first example of a sensor according to the presentinvention.

FIGS. 10 through 12 shows further process steps for producing a secondexample of a sensor according to the present invention;

FIG. 13 shows a further example of a sensor according to the presentinvention.

FIG. 14 shows a further sensor according to the present invention.

DETAILED DESCRIPTION

A process sequence elucidating the method of the present invention isshown in FIGS. 1 through 4. Shown in FIG. 1 is a cross-section of asilicon substrate 1, into which an opening 2 is introduced. Opening 2takes the form of a long, thin, blind hole, which typically has adiameter of less than 1 μm and extends more than 1 μm into the depth ofsilicon substrate 1. Silicon substrate 1 is, in particular, amonocrystalline silicon substrate. Such openings may be produced byreactive ion etching, i.e. irradiating the surface of silicon substrate1 with ions of a gas, which form a gaseous chemical compound with thesilicon material. Usually, the part of the surface of silicon substrate1 that should not be etched is protected by a masking of, for example,silicon oxide, silicon nitride, metals, or glass layers. A purelyablative, plasma-etching method may also be used as an alternative.

Silicon substrate 1, whose cross-section in shown in FIG. 1, is thensubjected to a temperature treatment. In this context, temperatures atwhich silicon atoms can be rearranged, i.e. temperatures greater than900° C., are selected. For example, a temperature treatment of 1100° C.is particularly suitable. Such a temperature treatment is preferablycarried out in a hydrogen atmosphere, since, in this case, oxide formingon the surface of silicon 1 may be removed from the surface of silicon 1and from the walls of opening 2. The high temperatures increase themobility of the silicon atoms, so that a rearrangement occurs in suchmanner, that the surface area of the silicon is reduced. As can be seenin FIG. 2, the result of this is that the diameter of opening 2decreases in the upper region of opening 2, i.e. in the region very nearthe surface of silicon substrate 1, and a hollow forms in the lowerregion of opening 2. When this method is continued for a while, thesituation shown in FIG. 3 occurs, i.e. a slight depression is stillpresent on the surface of silicon substrate 1, while a void 3 is formedin the interior of silicon substrate 1. However, such a void 3 is onlyformed, when opening 2, as shown in FIG. 1, is sufficiently deep andsufficiently narrow. Otherwise, in order to minimize the surfacetension, it is energetically more favorable when only a depression 4 isformed. Consequently, opening 2 must be sufficiently deep, and thecross-sectional area must be sufficiently small. It is at leastnecessary for the depth of opening 2 in silicon substrate 1 to begreater than the diameter of opening 2 at the surface. In FIG. 3, aminimum state with regard to the surface area is not yet reached. Thesurface of silicon substrate 1 still has a depression 4, and void 3still has an oval shape. However, this state is further changed bycontinuing the temperature treatment, and a nearly spherical void 3 isthen formed, over which there is also no more depression 4. This stateis shown in FIG. 4.

Therefore, it is possible to produce a void 3 in a silicon substrate 1,by introducing an opening 2 and carrying out a subsequent temperaturetreatment.

The method of the present invention is not limited to monocrystallinesilicon, but may equally be implemented in other semiconductormaterials, such as GaAs. In addition, polycrystalline semiconductormaterial may also be used. Semiconductors have the advantage thatconductive and nonconductive regions necessary for the manufacturing ofsensors may be produced by further processing steps.

When only hydrogen is trapped in the void, then an effective vacuum isproduced by a further temperature treatment, since the hydrogen easilydiffuses out through the silicon. This is especially of interest forpressure sensors, since a reference vacuum is consequently produced.Further temperature treatments are accomplished, for example, byintroducing and heat-treating dopants.

FIGS. 5 through 8 show how this method may produce a membrane that issituated over a void. Shown in FIG. 5 is a cross-section of siliconsubstrate 1, in which several openings 2 taking the form of narrow,deep, blind holes are introduced. A plan view of the substrate accordingto FIG. 5 is shown in FIG. 7. As can be seen in FIG. 7, several openings2 are spaced in close proximity to each other, the spacing of openings 2approximately corresponding to the diameter of openings 2. When FIGS. 5and 7 are used as a starting point and a temperature treatment iscarried out, silicon atoms are rearranged in each opening 2, as wasdescribed with regard to FIGS. 1 through 4. The result is a connected,large-area void 3, as is shown in FIG. 6 in a cross-section of siliconsubstrate 1. A membrane region 4, which is made up of a thin layer ofsilicon, is situated above areal void 3. When silicon substrate 1 is amonocrystalline silicon substrate, then this membrane 4 is formed, inturn, by monocrystalline silicon, since, during the rearrangement, thesilicon atoms position themselves at the proper crystal-lattice places.Therefore, the monocrystalline structure of silicon substrate 1 is alsomaintained in membrane region 4 over void 3. FIG. 8 shows a plan view,in which case it is clear that void 3 cannot be seen in a plan view.Therefore, areal void 3 represented in FIG. 8 may not be seen in theplan view but is nevertheless shown in FIG. 8, in order to give an ideaof how a void 3 is formed in the depth of the silicon substrate,starting out from visible openings 2 in FIG. 7.

In the configuration of openings 2, as is shown in FIGS. 5 and 7, thereis a correlation between the diameter of openings 2, the spacing ofopenings 2, and the depth of openings 2. The deeper openings 2 are putinto silicon substrate 1, the greater the distance may be betweenadjacent openings 2 in FIG. 7 in order to still produce a continuousvoid 3, as is shown in FIG. 8. If necessary, the exact size ratios ofthe diameter of openings 2, the spacing of openings 2 with respect toeach other, and the depth of openings 2 must be determinedexperimentally and may also be a function of further parameters, such asthe temperature of the temperature treatment, any introduced dopants,the composition of a protective gas during the temperature treatment,and the like.

However, in order to attain sensor patterns from the method described inFIGS. 1 through 8, further processing of silicon substrate 1 isnecessary.

FIG. 9 shows a first example of a sensor according to the presentinvention, which starts out from a silicon substrate 1, as isrepresented in FIGS. 6 and 8. Silicon substrate 1 has a void 3 and amembrane region 4 situated above it. Starting out from silicon substrate1, as is shown by way of example in FIGS. 6 through 8, an epitaxy layer11 is applied which covers the entire upper side of silicon substrate 1,including membrane region 4. Since silicon substrate 1 ismonocrystalline and the monocrystalline silicon structure is alsopresent in the region of membrane 4, epitaxy layer 11 grows in amonocrystalline manner. Typical thicknesses of such an epitaxy layer 11are on the order of several μm to several tens of μm. Dopants are thenintroduced on the upper side of epitaxy layer 11, using customarymethods. For example, doping zones 12 may be introduced forpiezoresistive resistor elements, which are then connected to contactopenings 14 of a passivation layer 15 by highly doped lead zones 13. Inthis context, piezoresistive resistor elements 12 are positioned to besituated in epitaxy layer 11 in the edge regions of void 3. Using highlydoped lead elements 13, electrical signals may then be tapped at contactopenings 14, via metallic conductor tracks (not shown). In particular,the electrical resistance of piezoresistive elements 13 may be measured.Because of their positioning relative to void 3, piezoresistive elements12 are in regions in which considerable mechanical stresses occur, incase epitaxy layer 11 and membrane region 4 deform above void 3. Suchdeformation may occur, for example, because the ambient pressuredeviates from the pressure trapped in void 3. Therefore, a device isprovided, which detects a change in the ambient pressure relative to thepressure in void 3, i.e. it is a pressure sensor. Using metallicconducting layers on the upper side of passivation layer 15, theelectrical signals of piezoresistive elements 12 may be supplied to anevaluation circuit 20, which is likewise formed in epitaxy layer 11 andsilicon substrate 1. For reasons of simplification, the metallicconductor tracks on the upper side of passivation layer 15 are notshown. In the same way, the electrical evaluation circuits are onlyindicated by diffusion zones 21, 22, and 23 and are by no meansequivalent to real circuit elements. Due to buried doping zone 21,dopant has already been introduced into the upper side of siliconsubstrate 1 prior to the deposition of epitaxy layer 11. Doping zones 22and 23 are customary doping zones introduced during the production ofcustomary semiconductor elements. In this context, processes are usedwhich are also used for producing piezoresistive elements 12 andhighly-doped leads 13. The method of the present invention for producingvoid 3 may easily be used with customary methods for producingsemiconductor patterns, so that both voids 3 and customary circuitelements 20 may be produced in one and the same process sequence. Anadditional manufacturing process for a pressure sensor is shown in FIGS.10, 11, and 12. However, in addition to the method steps described inFIGS. 1 through 8, dopant is also introduced into silicon substrate 1before and after the production of void 3. In this context, one startsout from a homogeneously doped silicon substrate, e.g. a p-doped siliconsubstrate, in which an opposite type of doping 30, e.g. n-doping, isthen introduced. Openings 2 are then introduced, as shown in FIGS. 5through 7. The region in which openings 2 are situated extends into bothp-doped substrate 1 and introduced n-doping 30. The depth of openings 2is less than the depth of doping 30, so that doping 30 is still foundunder openings 2. This state is shown in FIG. 10 a. The temperaturetreatment then produces a void 3, which extends into the interior ofsubstrate 1 and horizontally cuts through introduced n-doping 30, sothat the silicon above and below void 3 is n-doped. As it were, void 3cuts through the doping region in the horizontal direction. Thisproduces upper doping 31 and lower doping 32. By introducing a re-dopingzone 33 into the n-doped zones, i.e. by introducing a large number ofp-dopants, upper n-doping 31 and lower n-doping 32 may then beelectrically insulated from each other. Shown in FIG. 10 b is across-section of silicon substrate 1 produced in this manner, whereupper n-doping 31 is electrically insulated from lower n-doping 32 byvoid 3 and redoping zone 33. FIG. 11 shows a plan view of FIG. 10 b. Asis apparent, redoping 33 is positioned in such a manner, that it iselectrically situated between n-doping 32 and n-doping 31.Alternatively, redoping 33 may also be positioned in such a manner, thatit completely surrounds upper n-doping 31. In addition, FIGS. 10 and 11also show a doping zone 21 for a buried doping zone, which is customaryfor the production of bipolar circuits.

Starting out from FIGS. 10 and 11, an n-doped epitaxy layer 11 is thenapplied, in order to produce a sensor element. In this context, deepcontacting areas 35 und 36, which are also n-doped, are introduced intoepitaxy layer 11. In this case, deep contacting area 35 is positioned insuch a manner, that upper n-doping 31 is electrically contacted, anddeep contacting area 36 is positioned in such a manner, that lowern-doping 32 is electrically contacted. P-doped insulating rings 37 areproduced around deep contacting area 36 and around upper n-doping 31 toprovide mutual electrical insulation. A passivation layer 15, into whichcontact openings 14 are introduced, is then applied to the upper sideagain. Contact openings 14 are placed in such a manner, that deepcontacting areas 35 are contacted by metallic surface films not shown,so that an electrical surface connection may be made to circuit elements20, which are likewise formed in semiconductor substrate 1 and epitaxylayer 11. Semiconductor circuit elements 20 are, in turn, onlyschematically represented by buried doping zone 21 and further dopingzones 22 und 23.

The device shown in FIG. 12 represents a capacitive pressure sensor. Inthe event of a pressure difference between void 3 and the surroundings,epitaxy layer 11 and the region of semiconductor substrate 1 situatedabove void 3 deform. This changes the distance between upper doping zone31 and lower doping zone 32. Since these two zones are electricallyinsulated from each other, they form a plate-type capacitor, whosecapacitance is a function of the spacing of doping zones 31 and 32. Deepcontacting areas 35 and 36 allow this capacitance to be detected by anappropriate evaluation circuit. The level of deformation of epitaxylayer 11 and semiconductor substrate 1 may be inferred by measuring thecapacitance, and, in this manner, the ratio of the ambient pressure tothe pressure in void 3 may be determined. The capacitive measuringprincipal is particularly advantageous, since it is especiallyindependent of temperature. In addition, the capacitances may beevaluated in a particularly effective manner by circuits situated in theimmediate vicinity.

A further exemplary embodiment of a sensor according to the presentinvention is shown in FIG. 13. Using a substrate 1 represented in FIGS.6 and 8 as a starting point, an epitaxy layer 11 is applied. In thiscontext, a region above membrane 3 is provided with a high level ofdoping 50, so that epitaxy layer 11 is highly conductive in this region.In addition, high surface dopings 52 are introduced, which are used aselectrical leads to contact holes 14 in a passivation layer 15. Trenches51 are subsequently introduced by an etching process, which extends fromthe upper side of epitaxy layer 11 to void 3. In this manner, beamstructures 55 are produced, which may be geometrically designed to be,for example, movable by an acceleration parallel to the surface ofsubstrate 1. In addition, measures for insulating these beam structures55 among themselves and with respect to epitaxy layer 11 may also bedeveloped in edge regions not shown. In this manner, it is possible tomeasure capacitances between the beam structures and between beamstructures 55 and the rest of epitaxy layer 11, the capacitances being afunction of how much beam structures 55 are deformed. These capacitivesignals may then be transmitted, in turn, by metallized conductor tracksnot shown, to electronic circuits 20 also formed in epitaxy layer 11,via surface-doped conductive layers 52 and contact openings 14. In thismanner, a capacitive force sensor, e.g. an acceleration sensor, isproduced.

Shown in FIG. 14 is a further example of a sensor, which starts out froma substrate according to FIGS. 6 and 8. A movable element, in whichtrenches 51 extending to void 3 are introduced, is patterned out of anupper silicon layer, which is either formed out of only membrane layer4, or made of a corresponding epitaxy layer 11. In the plan view ofsilicon substrate 1 in FIG. 14, the boundaries of void 3 are representedby dotted line 62. Trenches 51 allow a seismic weight 71 suspended fromfour beam elements 72 to be formed out of the upper silicon layer.Piezoresistive elements 73 are situated on each of beam elements 72.These piezoresistive elements 73 allow the action of a force, inparticular an acceleration force acting on seismic weight 71, to bedetected, for when a force acts on weight 71, suspension arms 72 aredeformed and corresponding changes in the resistance of piezoresistiveelements 73 may be detected. In this case, both forces perpendicular tosubstrate 1 and forces parallel to the surface of the substrate may bedetected.

The advantage of the sensors shown in FIGS. 9 through 14 is that thesensor structures are all made of monocrystalline silicon. Therefore,piezoresistive resistor elements having high precision and long-termdurability may be introduced. In addition, movable elements made ofmonocrystalline silicon are of a particularly high quality and only showsmall aging effects. In addition, the method of the present inventionmay be completely integrated with customary semiconductor manufacturingprocesses, so that both bipolar circuits and CMOS circuits may beintegrated on the same substrate. In this manner, sensor elements andsemiconductor circuit elements may be jointly integrated on onesubstrate. Furthermore, only customary semiconductor manufacturingprocesses are used.

1. A method for manufacturing a micromechanical sensor, comprising:introducing openings into a semiconductor substrate; subsequentlyperforming a temperature treatment, wherein: geometric dimensions of theopenings and a temperature duration and a time duration of thetemperature treatment are selected in such a manner that a void forms ina depth of the semiconductor substrate; and providing a second layerabove the semiconductor substrate, wherein a sensing region is formed byat least one of a region of the substrate above the void and a region ofthe second layer above the void.
 2. The method as recited in claim 1,wherein: the temperature treatment is carried out at a temperaturegreater than 900° C.
 3. The method as recited in claim 1, wherein: thetemperature treatment is carried out a temperature greater than 1000° C.4. The method as recited in claim 1, wherein: the openings extend froman upper surface of the semiconductor substrate into the semiconductorsubstrate to the depth, and a spacing of side walls of the openings isless than a depth of the openings.
 5. The method as recited in claim 4,wherein: the openings at the upper surface of the semiconductorsubstrate are smaller than one μm in a direction and have a depthgreater than 2 μm.
 6. The method as recited in claim 1, whereinproviding the second layer includes depositing an epitaxy layer on asurface of the semiconductor substrate.
 7. The method as recited inclaim 6, further comprising: introducing dopants one of prior to andafter the deposition of the epitaxy layer.
 8. The method as recited inclaim 7, further comprising: forming piezoresistive elements in amonocrystalline semiconductor material by the dopants.
 9. The method asrecited in claim 8, wherein: the dopants are introduced into thesemiconductor substrate prior to introducing the openings.